New technologies, e.g., 32 nm and beyond, require features on a wafer with tighter pitch than can be directly patterned with state of the art and next generation lithography tools. The current solution to pattern such features involves printing half of the features on one mask, and half on another mask. This enables the pitch to be doubled. This doubling of pitch is designed to move the structure to within the operating range of current and next generation lithography tools.
More specifically, known pitch doubling techniques fall into two categories:                direct printing with two masks; and        self-aligned using sidewall image transfer.However, each of these fabrication methodologies have their own shortcomings.        
In the case of direct printing with two masks, non self-aligned pitch split techniques allow the patterning of arbitrary features, however, they suffer from overlay error between the two masks which is a persistent problem. The overlay error costs rework and drives significant variation in electrical properties. Currently, there is no solution that exists to prevent the overlay error.
Sidewall image transfer schemes, on the other hand, remove overlay sensitivity, but are extraordinarily restrictive in the features which can be patterned. The restriction in design space means that design scaling is jeopardized by the new restrictions from the self-aligned schemes.
Accordingly, there exists a need in the art to overcome the deficiencies and limitations described hereinabove.